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2 ADC, 8 DAC, 96 kHz, 24-Bit - Codecs AD1835A
FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports up to 96 kHz Sample Rates 192 kHz Sample Rate Available on 1 DAC Supports 16-/20-/24-Bit Word Lengths Multibit - Modulators with Perfect Differential Linearity Restoration for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs--Least Sensitive to Jitter Differential Output for Optimum Performance ADCs: -95 dB THD + N, 105 dB SNR, and Dynamic Range DACs: -95 dB THD + N, 108 dB SNR, and Dynamic Range On-Chip Volume Controls per Channel with 1024-Step Linear Scale DAC and ADC Software Controllable Clickless Mutes Digital De-emphasis Processing Supports 256 fS, 512 fS, and 768 fS Master Mode Clocks Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, LeftJustified, I2S Compatible, and DSP Serial Port Modes TDM Interface Mode Supports 8-In/8-Out Using a Single SHARC(R) SPORT 52-Lead MQFP Plastic Package APPLICATIONS DVD Video and Audio Players Home Theater Systems Automotive Audio Systems Audio/Visual Receivers Digital Audio Effects Processors PRODUCT OVERVIEW
The AD1835A is a high performance, single-chip codec featuring four stereo DACs and one stereo ADC. Each DAC comprises a high performance digital interpolation filter, a multibit - modulator featuring Analog Devices' patented technology, and a continuous-time voltage out analog section. (continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK PD/RST M/S AVDD AVDD
DLRCLK DBCLK DSDATA1 DSDATA2 DSDATA3 DSDATA4 SERIAL DATA I/O PORT
CONTROL PORT VOLUME VOLUME VOLUME VOLUME
CLOCK DAC OUTLP1 OUTLN1 OUTRP1 OUTRN1 OUTLP2 OUTLN2 OUTRP2 OUTRN2 OUTLP3 OUTLN3 OUTRP3 OUTRN3 OUTLP4 OUTLN4 OUTRP4 OUTRN4 FILTD FILTR
DIGITAL FILTER
DIGITAL FILTER
DAC
ADCLP ADCLN
ADC
DIGITAL FILTER
VOLUME VOLUME
DIGITAL FILTER
DAC
ADCRP ADCRN
ADC
DIGITAL FILTER
VOLUME VOLUME
DIGITAL FILTER
DAC
AD1835A
DGND DGND AGND AGND AGND AGND
VREF
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD1835A-SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock ADC Input Signal DAC Input Signal Input Sample Rate (fS) Measurement Bandwidth Word Width Load Capacitance Load Impedance
5.0 V 25C 12.288 MHz (256 fS Mode) 1.0078125 kHz, -1 dBFS (Full Scale) 1.0078125 kHz, 0 dBFS (Full Scale) 48 kHz 20 Hz to 20 kHz 24 Bits 100 pF 47 k
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter A-Weighted (48 kHz and 96 kHz) Total Harmonic Distortion + Noise (THD + N) 48 kHz 96 kHz Interchannel Isolation Interchannel Gain Mismatch Analog Inputs Differential Input Range ( Full Scale) Common-Mode Input Voltage Input Impedance Input Capacitance VREF DC Accuracy Gain Error Gain Drift DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Dynamic Range (20 Hz to 20 kHz, -60 dBFS Input) No Filter With A-Weighted Filter (48 kHz and 96 kHz) Total Harmonic Distortion + Noise (48 kHz and 96 kHz) Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Maximum Attenuation) Mute Attenuation De-emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance at Each Pin Common-Mode Output Voltage ADC DECIMATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay -2- Min Typ 24 100 103 105 -95 -95 100 0.025 -2.828 2.25 4 15 2.25 5 35 24 103 105 105 108 -95 110 4.0 0.025 200 -120 0.1 0.098 60 -100 0.1 1.0 (2.8) 180 2.25 21.77 0.01 26.23 120 910 -88.5 -87.5 Max Unit Bits dB dB dB dB dB dB V V k pF V % ppm/C Bits dB dB dB dB % dB ppm/C dB Degrees % dB dB dB V rms (V p-p) V kHz dB kHz dB s REV. A
+2.828
-90
AD1835A
Parameter ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 192 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current POWER SUPPLIES Supply Voltage (AVDD and DVDD) Supply Voltage (ODVDD) Supply Current IANALOG Supply Current IANALOG, Power-Down Supply Current IDIGITAL Supply Current IDIGITAL, Power-Down Dissipation Operation, Both Supplies Operation, Analog Supply Operation, Digital Supply Power-Down, Both Supplies Power Supply Rejection Ratio 1 kHz, 300 mV p-p Signal at Analog Supply Pins 20 kHz, 300 mV p-p Signal at Analog Supply Pins
*Guaranteed by design. Specifications subject to change without notice.
Min
Typ 43.54 0.01 52.46 120 460
Max
Unit kHz dB kHz dB s
21.77 0.06 28 55 340 43.54 0.06 52 55 160 81.2 0.06 97 80 110 2.4 0.8 ODVDD - 0.4 0.4 10 4.5 3.0 5.0 84 55 64 1 740 420 320 280 -70 -75 5.5 DVDD 95 67 74 4.5
kHz dB kHz dB s kHz dB kHz dB s kHz dB kHz dB s V V V V A V V mA mA mA mA mW mW mW mW dB dB
REV. A
-3-
AD1835A TIMING SPECIFICATIONS
Parameter MASTER CLOCK AND RESET MCLK High tMH tML MCLK Low tPDR PD/RST Low SPI(R) PORT tCCH tCCL tCCP tCDS tCDH tCLS tCLH tCOE tCOD tCOTS CCLK High CCLK Low CCLK Period CDATA Setup CDATA Hold CLATCH Setup CLATCH Hold COUT Enable COUT Delay COUT Three-State Min 15 15 20 40 40 80 10 10 10 10 15 20 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Comments
To CCLK Rising From CCLK Rising To CCLK Rising From CCLK Rising From CLATCH Falling From CCLK Falling From CLATCH Rising
DAC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Slave) DBCLK High tDBH DBCLK Low tDBL fDB DBCLK Frequency tDLS DLRCLK Setup DLRCLK Hold tDLH tDDS DSDATA Setup DSDATA Hold tDDH Packed 128/256 Modes (Slave) DBCLK High tDBH tDBL DBCLK Low DBCLK Frequency fDB tDLS DLRCLK Setup tDLH DLRCLK Hold DSDATA Setup tDDS tDDH DSDATA Delay ADC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Master) tABD ABCLK Delay ALRCLK Delay Low tALD ASDATA Delay tABDD Normal Mode (Slave) ABCLK High tABH ABCLK Low tABL fAB ABCLK Frequency tALS ALRCLK Setup ALRCLK Hold tALH tABDD ASDATA Delay Packed 128/256 Mode (Master) ABCLK Delay tPABD tPALD LRCLK Delay tPABDD ASDATA Delay
60 60 64 10 10 10 10 15 15 256 10 10 10 10
ns ns fS ns ns ns ns ns ns fS ns ns ns ns To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising
25 5 10 60 60 64 5 15
ns ns ns ns ns
From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge
fS 15 40 5 10 ns ns ns ns ns ns To ABCLK Rising From ABCLK Rising From ABCLK Falling Edge From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge
-4-
REV. A
AD1835A
Parameter TDM256 MODE (Master, 48 kHz and 96 kHz) tTBD BCLK Delay tFSD FSTDM Delay ASDATA Delay tTABDD DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold TDM256 MODE (Slave, 48 kHz and 96 kHz) BCLK Frequency fAB tTBCH BCLK High BCLK Low tTBCL FSTDM Setup tTFS tTFH FSTDM Hold ASDATA Delay tTBDD DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold TDM512 MODE (Master, 48 kHz) tTBD BCLK Delay FSTDM Delay tFSD ASDATA Delay tTABDD tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM512 MODE (Slave, 48 kHz ) fAB BCLK Frequency tTBCH BCLK High BCLK Low tTBCL tTFS FSTDM Setup FSTDM Hold tTFH ASDATA Delay tTBDD tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold AUXILIARY INTERFACE (48 kHz and 96 kHz) tAXDS AAUXDATA Setup AAUXDATA Hold tAXDH AUXBCLK Frequency fABP Slave Mode AUXBCLK High tAXBH AUXBCLK Low tAXBL tAXLS AUXLRCLK Setup AUXLRCLK Hold tAXLH Master Mode AUXLRCLK Delay tAUXLRCLK tAUXBCLK AUXBCLK Delay
Specifications subject to change without notice.
Min
Max 40 5 10
Unit ns ns ns ns ns
Comments From MCLK Rising From BCLK Rising From BCLK Rising To BCLK Falling From BCLK Falling
15 15 256 17 17 10 10 15 15 40 5 10 15 15 512 17 17 10 10 15 15 10 10 64 15 15 10 10 15 20 fS fS
15
ns ns ns ns ns ns ns ns ns ns ns ns
To BCLK Falling From BCLK Falling From BCLK Rising To BCLK Falling From BCLK Falling From MCLK Rising From BCLK Rising From BCLK Rising To BCLK Falling From BCLK Falling
15
ns ns ns ns ns ns ns ns ns
To BCLK Falling From BCLK Falling From BCLK Rising To BCLK Falling From BCLK Falling To AUXBCLK Rising From AUXBCLK Rising
fS ns ns ns ns ns ns
To AUXBCLK Rising From AUXBCLK Rising From AUXBCLK Falling From MCLK Rising
tMH
MCLK
tMCLK
tML
PD/RST
tPDR
Figure 1. MCLK and PD/ RST Timing
REV. A
-5-
AD1835A
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
TEMPERATURE RANGE
AVDD, DVDD, ODVDD to AGND, DGND . . -0.3 V to +6.0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . -0.3 V to ODVDD + 0.3 V Analog I/O Voltage to AGND . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . -40C to +85C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter Specifications Guaranteed Functionality Guaranteed Storage
Min -40 -65
Typ 25
Max +85 +150
Unit C C C
ORDERING GUIDE
Model AD1835AAS AD1835AAS-REEL AD1835AASZ* AD1835AASZ-REEL* EVAL-AD1835AEB
*Z = Pb-free part.
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP Evaluation Board
Package Option S-52-1 S-52-1 S-52-1 S-52-1
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1835A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-6-
REV. A
AD1835A
PIN CONFIGURATION
DSDATA4 DSDATA3 DSDATA2 DSDATA1
41
ASDATA
ALRCLK
ODVDD
ABCLK
DGND
52
51
50
49
48
47
46
45
44
43
42
40
DGND
39 DVDD 38 DBCLK 37 DLRCLK 36 M/S 35 AGND 34 OUTRP4 33 OUTRN4 32 OUTLP4 31 OUTLN4 30 AGND 29 AVDD 28 OUTRP3 27 OUTRN3
26
DVDD CLATCH CIN PD/RST AGND OUTLN1 OUTLP1 OUTRN1 OUTRP1
1 2 3 4 5 6 7 8 9
AD1835A
TOP VIEW (Not to Scale)
AGND 10 AVDD 11 OUTLN2 12 OUTLP2 13
14 15 16 17 18 19 20 21 22 23 24 25
OUTRN2
AGND
MCLK
COUT
CCLK
ADCRN
ADCRP
AGND
OUTLN3
OUTRP2
PIN FUNCTION DESCRIPTIONS
Pin Number 1, 39 2 3 4 5, 10, 16, 24, 30, 35 6, 12, 25, 31 7, 13, 26, 32 8, 14, 27, 33 9, 15, 28, 34 11, 19, 29 17 18 20 21 22 23 36 37 38 40, 52 41 to 44 45 46 47 48 49 50 51 REV. A
Mnemonic DVDD CLATCH CIN PD/RST AGND OUTLNx OUTLPx OUTRNx OUTRPx AVDD FILTD FILTR ADCLN ADCLP ADCRN ADCRP M/S DLRCLK DBCLK DGND DSDATAx ABCLK ALRCLK MCLK ODVDD ASDATA COUT CCLK
Input/ Output I I I O O O O
Description Digital Power Supply. Connect to digital 5 V supply. Latch Input for Control Data. Serial Control Input. Power-Down/Reset. Analog Ground. DACx Left Channel Negative Output. DACx Left Channel Positive Output. DACx Right Channel Negative Output. DACx Right Channel Positive Output. Analog Power Supply. Connect to analog 5 V supply. Filter Capacitor Connection. Recommended 10 F/100 nF. Reference Filter Capacitor Connection. Recommended 10 F/100 nF. ADC Left Channel Negative Input. ADC Left Channel Positive Input. ADC Right Channel Negative Input. ADC Right Channel Positive Input. ADC Master/Slave Select. DAC LR Clock. DAC Bit Clock. Digital Ground. DACx Input Data (Left and Right Channels). ADC Bit Clock. ADC LR Clock. Master Clock Input. Digital Output Driver Power Supply. ADC Serial Data Output. Output for Control Data. Control Clock Input for Control Data. -7-
I I I I I I/O I/O I I/O I/O I O O I
OUTLP3
ADCLN
AVDD
ADCLP
FILTD
FILTR
AD1835A-Typical Performance Characteristics
0 5 0 -50
MAGNITUDE - dB
-5
MAGNITUDE - dB
0 5 10 15
-10
-100
-15 -20
-150
-25 -30 0 5 10 FREQUENCY - Hz 15 20
FREQUENCY - Normalized to fS
TPC 1. ADC Composite Filter Response
TPC 4. ADC High-Pass Filter Response, fS = 96 kHz
5 0 -5
0
MAGNITUDE - dB
MAGNITUDE - dB
0 5 10 FREQUENCY - Hz 15 20
-50
-10
-15 -20 -25 -30
-100
-150
0
50
100 FREQUENCY - kHz
150
200
TPC 2. ADC High-Pass Filter Response, fS = 48 kHz
TPC 5. DAC Composite Filter Response, fS = 48 kHz
0
0
MAGNITUDE - dB
MAGNITUDE - dB
-50
-50
-100
-100
-150 0 0.5 1.0 1.5 2.0 FREQUENCY - Normalized to fS
-150
0
50
100 FREQUENCY - kHz
150
200
TPC 3. ADC Composite Filter Response (Pass-Band Section)
TPC 6. DAC Composite Filter Response, fS = 96 kHz
-8-
REV. A
AD1835A
0
0.2
-50
MAGNITUDE - dB
MAGNITUDE - dB
0.1
0
-100
-0.1
-150
0
50
100 FREQUENCY - kHz
150
200
-0.2
0
10
20 30 FREQUENCY - kHz
40
50
TPC 7. DAC Composite Filter Response, fS = 192 kHz
TPC 9. DAC Composite Filter Response, fS = 96 kHz (Pass-Band Section)
0.10
0.10
0.05 MAGNITUDE - dB
0.05
0
MAGNITUDE - dB
0 5 10 FREQUENCY - kHz 15 20
0
-0.05
-0.05
-0.10
-0.10
0
20
40 60 FREQUENCY - kHz
80
100
TPC 8. DAC Composite Filter Response, fS = 48 kHz (Pass-Band Section)
TPC 10. DAC Composite Filter Response, fS = 192 kHz (Pass-Band Section)
REV. A
-9-
AD1835A
DEFINITIONS Dynamic Range Gain Drift
The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a -60 dB input signal and is equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics are below the noise with a -60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-weight filter applied.
Signal-to-(Total Harmonic Distortion + Noise)[S/(THD + N)]
Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels.
Power Supply Rejection
The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels (dB).
Pass Band
With no analog input, signal present at the output when a 300 mV p-p signal is applied to power supply pins, expressed in decibels of full scale.
Group Delay
The region of the frequency spectrum unaffected by the attenuation of the digital decimator's filter.
Pass-Band Ripple
Intuitively, the time interval required for an input pulse to appear at the converter's output, expressed in microseconds. More precisely, the derivative of radian phase with respect to radian frequency at a given frequency.
Group Delay Variation
The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels.
Stop Band
The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds.
GLOSSARY
The region of the frequency spectrum attenuated by the digital decimator's filter to the degree specified by stop-band attenuation.
Gain Error
With a near full-scale input, the ratio of actual output to expected output, expressed as a percentage.
Interchannel Gain Mismatch
ADC--Analog-to-Digital Converter. DAC--Digital-to-Analog Converter. DSP--Digital Signal Processor. IMCLK--Internal Master Clock Signal Used to Clock the ADC and DAC Engines. MCLK--External Master Clock Signal Applied to the AD1835A.
With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels.
-10-
REV. A
AD1835A
(continued from page 1) Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit - modulators and decimation filters. The AD1835A also contains an on-chip reference with a nominal value of 2.25 V. The AD1835A contains a flexible serial interface that allows glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1835A can be configured in left-justified, right-justified, I2S, or DSP compatible serial modes. Control of the AD1835A is achieved by an SPI(R) compatible serial port. While the AD1835A can be operated from a single 5 V supply, it also features a separate supply pin for its digital interface which allows the device to be interfaced to other devices using 3.3 V power supplies. The AD1835A is available in a 52-lead MQFP package and is specified for the industrial temperature range of -40C to +85C.
FUNCTIONAL OVERVIEW ADCs
high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD pin should be connected to an external grounded capacitor. This pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. In some cases, this capacitor may be eliminated with little effect on performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement encoded format. The word width can be selected from 16 bit, 20 bit, or 24 bit. The coding scheme is detailed in Table I.
Table I. Coding Scheme
Code 01111......1111 00000......0000 10000......0000
AD1835A CLOCKING SCHEME
Level +FS 0 (Ref Level) -FS
There are two ADC channels in the AD1835A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate of up to 96 kHz. The ADCs include on-board digital decimation filters with 120 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz operation). ADC peak level information for each ADC may be read from the ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a 6-bit word with a maximum range of 0 dB to -63 dB and a resolution of 1 dB. The registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. Refer to the register description for details of the format. The two ADC channels have a common serial bit clock and a left-right framing clock. The clock signals are all synchronous with the sample rate. The ADC digital pins, ABCLK and ALRCLK, can be set to operate as inputs or outputs by connecting the M/S pin to ODVDD or DGND, respectively. When the pins are set as outputs, the AD1835A will generate the timing signals. When the pins are set as inputs, the timing must be generated by the external audio controller.
DACs
By default, the AD1835A requires an MCLK signal that is 256 times the required sample frequency up to a maximum of 12.288 MHz. The AD1835A uses a clock scaler to double the clock frequency for use internally. The default setting of the clock scaler is Multiply by 2. The clock scaler can also be set Multiply by 1 (bypass) or by 2/3. The clock scaler is controlled by programming the bits in the ADC Control 3 register. The internal MCLK signal, IMCLK, should not exceed 24.576 MHz in order to ensure correct operation. The MCLK of the AD1835A should remain constant during normal operation of the DAC and ADC. If it is necessary to change the MCLK rate, then the AD1835A should be reset. Additionally, if the MCLK scaler needs to be modified so that the IMCLK doesn't exceed 24.576 MHz, this should be done during the internal reset phase of the AD1835A by programming the bits in the first 3072 MCLK periods following the reset.
Selecting DAC Sampling Rate
The AD1835A has eight DAC channels arranged as four independent stereo pairs, with eight fully differential analog outputs for improved noise and distortion performance. Each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one of the packed data modes can be used to access all eight channels on a single TDM data pin. A stereo replicate feature is included where the DAC data sent to the first DAC pair is also sent to the other DACs in the part. The AD1835A can accept DAC data at a sample rate of 192 kHz on DAC 1 only. The stereo replicate feature can then be used to copy the audio data to the other DACs. Each set of differential output pins sits at a dc level of VREF and swings 1.4 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove REV. A
The AD1835A DAC engine has a programmable interpolator that allows the user to select different interpolation rates based on the required sample rate and MCLK value available. Table II shows the settings required for sample rates based on a fixed MCLK of 12.288 MHz.
Table II. DAC Sample Rate Settings
Sample Rate Interpolator Rate DAC Control 1 Register 48 kHz 96 kHz 192 kHz 8x 4x 2x 000000xxxxxxxx00 000000xxxxxxxx01 000000xxxxxxxx10
Selecting an ADC Sample Rate
The AD1835A ADC engine has a programmable decimator, which allows the user to select the sample rate based on the MCLK value. By default, the output sample rate is IMCLK/ 512. To achieve a sample rate of IMCLK/256, the sample rate bit in the ADC Control 1 register should be set as shown in Table III.
-11-
AD1835A
DAC ENGINE 48kHz/96kHz/192kHz INTERPOLATION FILTER - MODULATOR ANALOG OUTPUT DAC I/P DAC
CLOCK SCALING 1 MCLK 12.288MHz 2/3 2 IMCLK = 24.576MHz
ADC ENGINE 48kHz/96kHz OPTIONAL HPF DECIMATOR / FILTER - MODULATOR ANALOG INPUT
ADC O/P
Figure 2. Modulator Clocking Scheme
tCLS
CLATCH
tCCP
tCCH tCCL
tCLH tCOTS
CCLK
tCDS tCDH
CIN D15 D14 D9 D8 D0
COUT
tCOE
D9
D8
D0
tCOD
Figure 3. Format of SPI Timing
Table III. ADC Sample Rate Settings Power Supply and Voltage Reference
Sample Rate IMCLK/512 IMCLK/256
ADC Control 1 Register 1100000xx0xxxxxx (48 kHz) 1100000xx1xxxxxx (96 kHz)
To maintain the highest performance possible, the clock jitter of the master clock signal should be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. It is highly recommended that the master clock be generated by an independent crystal oscillator. In addition, it is especially important that the clock signal not be passed through an FPGA or other large digital chip before being applied to the AD1835A. In most cases, this will induce clock jitter due to the fact that the clock signal is sharing common power and ground connections with unrelated digital output signals.
RESET and Power-Down
The AD1835A is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 F should also be provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by two ferrite beads in series with the bypass capacitor of each supply. It is important that the analog supply be as clean as possible. The internal voltage reference is brought out on the FILTR pin and should be bypassed as close as possible to the chip, with a parallel combination of 10 F and 100 nF. The reference voltage may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. The current drawn from the VREF pin should be limited to less than 50 A.
PD/RST will power down the chip and set the control registers Serial Control Port to their default settings. After PD/RST is de-asserted, an The AD1835A has an SPI compatible control port to permit initialization routine will run inside the AD1835A to clear all programming the internal control registers for the ADCs and memories to zero. This initialization lasts approximately 20 DACs and for reading the ADC signal levels from the internal LRCLK intervals. During this time, it is recommended that no peak detectors. The SPI control port is a 4-wire serial control port. SPI writes occur. -12- REV. A
AD1835A
The format is similar to the Motorola SPI format except the input data-word is 16 bits wide. The maximum serial bit clock frequency is 12.5 MHz and may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 3 shows the format of the SPI signal.
Serial Data Ports--Data Format
data pin. DAC data is applied on the DSDATA1 pin and ADC data is available on the ASDATA pin. Figures 7 to 12 show the timing for the packed mode. Packed mode is available for 48 kHz and 96 kHz.
Auxiliary (TDM) Mode
The ADC serial data output mode defaults to the popular I2S format, where the data is delayed by 1 BCLK interval from the edge of the LRCLK. By changing Bits 6 to 8 in ADC Control Register 2, the serial mode can be changed to right-justified (RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ mode, it is necessary to set Bits 4 and 5 to define the width of the data-word. The DAC serial data input mode defaults to I2S. By changing Bits 5, 6, and 7 in DAC Control Register 1, the mode can be changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2. The word width defaults to 24 bits but can be changed by reprogramming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
A special auxiliary mode is provided to allow three external stereo ADCs to be interfaced to the AD1835A to provide 8-in/8-out operation. In addition, this mode supports glueless interface to a single SHARC DSP serial port, allowing a SHARC DSP to access all eight channels of analog I/O. In this special mode, many pins are redefined; see Table IV for a list of redefined pins. The auxiliary and TDM interfaces are independently configurable to operate as masters or slaves. When the auxiliary interface is set as a master, by programming the auxiliary mode bit in ADC Control Register 2, the AUXLRCLK and AUXBCLK are generated by the AD1835A. When the auxiliary interface is set as a slave, the AUXLRCLK and AUXBCLK need to be generated by an external ADC as shown in Figure 15. The TDM interface can be set to operate as a master or slave by connecting the M/S pin to DGND or ODVDD, respectively. In master mode, the FSTDM and BCLK signals are outputs and are generated by the AD1835A. In slave mode, the FSTDM and BCLK are inputs and should be generated by the SHARC. Both 48 kHz and 96 kHz operations are available (based on a 12.288 MHz or 24.576 MHz MCLK) in this mode.
The AD1835A has a packed mode that allows a DSP or other controller to write to all DACs and read all ADCs using one input data pin and one output data pin. Packed Mode 256 refers to the number of BCLKs in each frame. The LRCLK is low while data from a left channel DAC or ADC is on the data pin and high while data from a right channel DAC or ADC is on the
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
LEFT-JUSTIFIED MODE - 16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB I2S
MSB
LSB
MODE - 16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE - SELECT NUMBER OF BITS PER CHANNEL
LRCLK BCLK SDATA MSB LSB MSB LSB
DSP MODE - 16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 fS. 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 4. Stereo Serial Modes
REV. A
-13-
AD1835A
tABH
ABCLK
tABL tALS
ALRCLK
tABDD
tALH
ASDATA LEFT-JUSTIFIED MODE
MSB
MSB - 1
ASDATA I2S COMPATIBLE MODE
MSB
ASDATA RIGHT-JUSTIFIED MODE
MSB
LSB
Figure 5. ADC Serial Mode Timing
tDBH
DBCLK
tDBL tDLS
DLRCLK
tDLH
DSDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB - 1
tDDH
DSDATA I2S COMPATIBLE MODE
tDDS
MSB
tDDH
DSDATA RIGHT-JUSTIFIED MODE
tDDS
MSB
tDDS
LSB
tDDH
tDDH
Figure 6. DAC Serial Mode Timing
-14-
REV. A
AD1835A
LRCLK 128 BCLKs BCLK 16 BCLKs ADC DATA SLOT 1 LEFT SLOT 2 SLOT 3 SLOT 4 SLOT 5 RIGHT SLOT 6 SLOT 7 SLOT 8 ALRCLK ABCLK
tABH
tABL tALS
tALH
tABDD
MSB MSB - 1
ASDATA MSB MSB - 1 MSB - 2
Figure 7. ADC Packed Mode 128
LRCLK 256 BCLKs BCLK 32 BCLKs ADC DATA SLOT 1 LEFT SLOT 2 SLOT 3 SLOT 4 SLOT 5 RIGHT SLOT 6 SLOT 7 SLOT 8
Figure 11. ADC Packed Mode Timing
tDBH
DBCLK
tDBL tDLS
DLRCLK
tDLH tDDS
MSB MSB - 1 MSB - 2
DSDATA MSB MSB - 1
Figure 8. ADC Packed Mode 256
LRCLK 128 BCLKs BCLK 16 BCLKs DAC DATA SLOT 1 LEFT 1 SLOT 2 LEFT 2 SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
tDDH
Figure 12. DAC Packed Mode Timing
MSB
MSB - 1
MSB - 2
Figure 9. DAC Packed Mode 128
LRCLK 256 BCLKs BCLK 32 BCLKs DAC DATA SLOT 1 LEFT 1 SLOT 2 LEFT 2 SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
MSB
MSB - 1
MSB - 2
Figure 10. DAC Packed Mode 256
REV. A
-15-
AD1835A
Table IV. Pin Function Changes in Auxiliary Mode
Pin Name ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) DSDATA4 (I)/AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK(I/O) DBCLK (I)/AUXBCLK(I/O)
I2S Mode I S Data Out, Internal ADC I2S Data In, Internal DAC1 I2S Data In, Internal DAC2 I2S Data In, Internal DAC3 I2S Data In, Internal DAC4 LRCLK for ADC BCLK for ADC LRCLK In/Out Internal DACs BCLK In/Out Internal DACs
2
Auxiliary Mode TDM Data Out to SHARC. TDM Data In from SHARC. AUX-I2S Data In 1 (from External ADC). AUX-I2S Data In 2 (from External ADC). AUX-I2S Data In 3 (from External ADC). TDM Frame Sync Out to SHARC (FSTDM). TDM BCLK Out to SHARC. AUX LRCLK In/Out. Driven by external LRCLK from ADC in slave mode. In master mode, driven by MCLK/512. AUX BCLK In/Out. Driven by external BCLK from ADC in slave mode. In master mode, driven by MCLK/8.
FSTDM
BCLK TDM
MSB TDM MSB TDM
8TH CH
TDM INTERFACE
ASDATA1 TDM (OUT)
1ST CH
ASDATA
INTERNAL ADC L1
AUX_ADC L2
AUX_ADC L3
AUX_ADC L4
INTERNAL ADC R1
AUX_ADC R2
AUX_ADC R3
AUX_ADC R4
32
MSB TDM MSB TDM
8TH CH
DSDATA1 TDM (IN)
1ST CH
DSDATA1
INTERNAL DAC L1
INTERNAL DAC L2
INTERNAL DAC L3
INTERNAL DAC L4
INTERNAL DAC R1
INTERNAL DAC R2
INTERNAL DAC R3
INTERNAL DAC R4
32
AUX LRCLK I2S (FROM AUX ADC No. 1) AUX BCLK I2S (FROM AUX ADC No. 1) AAUXDATA1 (IN) (FROM AUX ADC No. 1) AAUXDATA2 (IN) (FROM AUX ADC No. 2)
LEFT
RIGHT
AUX - I2S INTERFACE
I2S - MSB LEFT
I2S - MSB RIGHT
I2S - MSB LEFT
I2S - MSB RIGHT
AAUXDATA3 (IN) (FROM AUX ADC No. 3)
I2S - MSB LEFT
I2S - MSB RIGHT
AUX BCLK FREQUENCY IS 64
FRAME RATE; TDM BCLK FREQUENCY IS 256
FRAME RATE.
Figure 13. Auxiliary Mode Timing
-16-
REV. A
AD1835A
30MHz
TFS (NC)
RxDATA
RxCLK
LRCLK ADC No. 1 BCLK SLAVE DATA MCLK
LRCLK ADC No. 2 BCLK SLAVE DATA MCLK DBCLK/AUXBCLK DLRCLK/AUXLRCLK LRCLK ADC No. 3 BCLK SLAVE DATA MCLK DSDATA2/AAUXDATA1 DSDATA3/AAUXDATA2 DSDATA4/AAUXDATA3 MCLK ASDATA FSTDM BCLK DSDATA1
AD1835A MASTER
Figure 14. Auxiliary Mode Connection (Master Mode) to SHARC
30MHz
TxDATA
SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN). DSDATA1
12.288MHz
FSYNC-TDM (RFS)
SHARC
SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN).
TFS (NC)
RxDATA
RxCLK
LRCLK ADC No. 1 BCLK MASTER DATA MCLK
LRCLK ADC No. 2 SLAVE BCLK DATA MCLK DBCLK/AUXBCLK LRCLK ADC No. 3 BCLK SLAVE DATA MCLK DLRCLK/AUXLRCLK DSDATA2/AAUXDATA1 DSDATA3/AAUXDATA2 DSDATA4/AAUXDATA3 MCLK ASDATA FSTDM BCLK
AD1835A SLAVE
Figure 15. Auxiliary Mode Connection (Slave Mode) to SHARC
REV. A
-17-
TxDATA
12.288MHz
FSYNC-TDM (RFS)
SHARC
TxCLK
TxCLK
AD1835A
CONTROL/STATUS REGISTERS DAC Volume Control
The AD1835A has 15 control registers, 13 of which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each of the registers is 10 bits wide with the exception of the ADC peak reading registers, which are six bits wide. Writing to a control register requires a 16-bit data frame to be transmitted. Bits 15 to 12 are the address bits of the required register. Bit 11 is a read/write bit. Bit 10 is reserved and should always be programmed to 0. Bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. Figure 3 shows the format of the SPI read and write operation.
DAC Control Registers
Each DAC in the AD1835A has its own independent volume control. The volume of each DAC can be adjusted in 1024 linear steps by programming the appropriate register. The default value for this register is 1023, which provides no attenuation, i.e., full volume.
ADC Control Registers
The AD1835A register map has five registers that are used to control the functionality and read the status of the ADCs. The function of the bits in each of these registers is discussed in the following sections.
ADC Peak Level
The AD1835A register map has 10 registers that are used to control the functionality of the DAC section of the part. The function of the bits in these registers is discussed in the following sections.
Sample Rate
These bits control the sample rate of the DACs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and 192 kHz are available. The MCLK scaling bits in ADC Control 3 should be programmed appropriately, based on the master clock frequency.
Power-Down/Reset
These two registers store the peak ADC result from each channel when the ADC peak readback function is enabled. The peak result is stored as a 6-bit number from 0 dB to -63 dB in 1 dB steps. The value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. Note that the ADC peak level registers use the six most significant bits in the register to store the results.
Sample Rate
This bit controls the power-down status of the DAC section. By default, normal mode is selected, but by setting this bit, the digital section of the DAC stage can be put into a low power mode, thus reducing the digital current. The analog output section of the DAC stage is not powered down.
DAC Data-Word Width
This bit controls the sample rate of the ADCs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are available. The MCLK scaling bits in ADC Control 3 should be programmed appropriately based on the master clock frequency.
ADC Power-Down
This bit controls the power-down status of the ADC section and operates in a manner similar to the DAC power-down.
High-Pass Filter
These two bits set the word width of the DAC data. Compact disk (CD) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution.
DAC Data Format
The ADC signal path has a digital high-pass filter. Enabling this filter will remove the effect of any dc offset in the analog input signal from the digital output codes.
ADC Data-Word Width
The AD1835A serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Details of these interface modes are given in the Serial Data Port section.
De-emphasis
These two bits set the word width of the ADC data.
ADC Data Format
The AD1835A serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes.
Master/Slave Auxiliary Mode
The AD1835A provides built-in de-emphasis filtering for the three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
Mute DAC
Each of the eight DACs in the AD1835A has its own independent mute control. Setting the appropriate bit will mute the DAC output. The AD1835A uses a clickless mute function that attenuates the output to approximately -100 dB over a number of cycles.
Stereo Replicate
When the AD1835A is operating in the auxiliary mode, the auxiliary ADC control pins, AUXBCLK and AUXLRCLK, which connect to the external ADCs, can be set to operate as a master or slave. If the pins are set in slave mode, one of the external ADCs should provide the LRCLK and BCLK signals.
ADC Peak Readback
Setting this bit copies the digital data sent to the stereo pair DAC1 to the three other stereo DACs in the system. This allows all four stereo DACs to be driven by one digital data stream. Note that in this mode, DAC data sent to the other DACs is ignored.
Setting this bit enables ADCs peak reading. See the ADCs section for more information.
-18-
REV. A
AD1835A
Table V. Control Register Map
Register Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Register Name DACCTRL1 DACCTRL2 DACVOL1 DACVOL2 DACVOL3 DACVOL4 DACVOL5 DACVOL6 DACVOL7 DACVOL8 ADCPeak0 ADCPeak1 ADCCTRL1 ADCCTRL2 ADCCTRL3 Reserved
Description DAC Control 1 DAC Control 2 DAC Volume-Left 1 DAC Volume-Right 1 DAC Volume-Left 2 DAC Volume-Right 2 DAC Volume-Left 3 DAC Volume-Right 3 DAC Volume-Left 4 DAC Volume-Right 4 ADC Left Peak ADC Right Peak ADC Control 1 ADC Control 2 ADC Control 3 Reserved
Table VI. DAC Control 1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W
Width 10 10 10 10 10 10 10 10 10 10 6 6 10 10 10 10
Reset Setting (Hex) 000 000 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 000 000 000 000 000 Reserved
Function Address DAC Data R/W RES De-emphasis Format 10 0 9, 8 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz 7, 6, 5 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Packed 128 110 = Reserved 111 = Reserved DAC DataWord Width 4, 3 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved Power-Down Reset 2 Sample Rate 1, 0 (48 kHz) (96 kHz) (192 kHz) (48 kHz)
15, 14, 13, 12 11 0000 0
0 = Normal 00 = 8 1 = Power-Down 01 = 4 10 = 2 11 = 8
Table VII. DAC Control 2
Function
Stereo Address R/W RES Reserved Replicate MUTE DAC OUTR4 OUTL4 OUTR3 OUTL3 OUTR2 OUTL2 OUTR1
OUTL1
15, 14, 13, 12 0001
11 0
10 0
9 0
8
7
6
5
4
3
2
1
0
0 = Off 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 1 = Replicate 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute
REV. A
-19-
AD1835A
Table VIII. DAC Volume Control Table IX. ADC Peak
Address 15, 14, 13, 12 0010 = DACL1 0011 = DACR1 0100 = DACL2 0101 = DACR2 0110 = DACL3 0111 = DACR3 1000 = DACL4 1001 = DACR4
R/W 11 0
RES 10 0
Function DAC Volume 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0000000000 = Mute 0000000001 = 1/1023 0000000010 = 2/1023 1111111110 = 1022/1023 1111111111 = 1023/1023 Address 15, 14, 13, 12 11 10 0
Function R/W RES Six Data Bits 9, 8, 7, 6, 5, 4 Four Fixed Bits 3, 2, 1, 0
1010 = Left ADC 1 1011 = Right ADC
000000 = 0.0 dBFS 0000 000001 = -1.0 dBFS 000010 = -2.0 dBFS These four 111111 = -63.0 dBFS bits are always zero.
Table X. ADC Control 1
Address 15, 14, 13, 12 1100
R/W 11 0
RES 10 0
RES 9 0
Filter 8 0 = All Pass 1 = High-Pass
Function ADC Power-Down 7 0 = Normal 1 = Power-Down
Sample Rate 6 0 = 48 kHz 1 = 96 kHz
Reserved 5, 4, 3, 2, 1, 0 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0
Table XI. ADC Control 2
Function Address 15, 14, 13, 12 1101 R/W RES 11 0 RES 10 0 Master/Slave ADC Aux Mode Data Format 9 0 = Slave 1 = Master 8, 7, 6 000 = I S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Packed 128 110 = Auxiliary 256 111 = Auxiliary 512
2
ADC DataWord Width 5, 4 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved
ADC MUTE Reserved 3, 2 0, 0 Right 1 0 = On 1 = Mute Left 0 0 = On 1 = Mute
Table XII. ADC Control 3
Function Address R/W IMCLK ADC RES RES Reserved Clocking Scaling Peak Readback 10 0 9 0, 0 8, 7, 6 00 = MCLK 01 = MCLK 10 = MCLK 11 = MCLK 2 2/3 2 5 DAC Test Mode 4, 3, 2 ADC Test Mode 1, 0
15, 14, 13, 12 11 1110 0
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode 1 = Enabled Peak Readback All others reserved All others reserved
-20-
REV. A
AD1835A
CASCADE MODE Dual AD1835A Cascade
The AD1835A can be cascaded to an additional AD1835A which, in addition to six external stereo ADCs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. The cascade is designed to connect to a SHARC DSP and operates in a time division multiplexing (TDM) format. Figure 16 shows the connection diagram for cascade operation. The digital interface for both parts must be set to operate in Auxiliary 512 mode by programming ADC Control Register 2. AD1835A No. 1 is set as a master device by connecting the M/S pin to DGND and AD1835A No. 2 is set as a slave device by connecting the M/S to ODVDD. Both devices should be run from the same MCLK and PD/RST signals to ensure that they are synchronized.
With Device 1 set as a master it will generate the frame-sync and bit clock signals. These signals are sent to the SHARC and Device 2, ensuring that both know when to send and receive data. The cascade can be thought of as two 256 bit shift registers, one for each device. At the beginning of a sample interval, the shift registers contain the ADC results from the previous sample interval. The first shift register (Device 1) clocks data into the SHARC and clocks in data from the second shift register (Device 2). While this is happening, the SHARC is sending DAC data to the second shift register. By the end of the sample interval, all 512 bits of ADC data in the shift registers will have been clocked into the SHARC and replaced by DAC data, which is subsequently written to the DACs. Figure 17 shows the timing diagram for the cascade operation.
AUX ADC (SLAVE) LRCLK DOUT BCLK
AUX ADC (SLAVE) LRCLK DOUT BCLK
AUX ADC (SLAVE) LRCLK DOUT BCLK
AUX ADC (SLAVE) LRCLK DOUT BCLK
AUX ADC (SLAVE) LRCLK DOUT BCLK
AUX ADC (SLAVE) LRCLK DOUT BCLK
R3 R4 R3 R4
AUXLRCLK AUXDATA1 AUXDATA2 AUXDATA3
AUXLRCLK AUXDATA1 AUXDATA2 AUXDATA3
AUXBCLK
AUXBCLK
AD1835A No. 1 (MASTER)
AD1835A No. 2 (SLAVE)
SHARC (SLAVE)
DRx RFSx RCLKx TFSx TCLKx DTx
ASDATA ALRCLK ABCLK
DSDATA
ASDATA ALRCLK ABCLK
DSDATA
Figure 16. Dual AD1835A Cascade
256 ABCLKs TFSx/ RFSx AD1835A No. 1 DACs DTx L1 L2 L3 L4 R1 R2 R3 R4 L1 L2
256 ABCLKs
AD1835A No. 2 DACs L3 L4 R1 R2
AD1835A No. 1 ADCs DRx L1 L2 L3 L4 R1 R2 R3 R4 L1 L2
AD1835A No. 2 ADCs L3 L4 R1 R2
ABCLK DTx DRx MSB MSB MSB - 1 MSB - 1 LSB LSB 32 ABCLKs DON'T CARE
Figure 17. Dual AD1835A Cascade Timing
REV. A
-21-
AD1835A
AUDIO INPUT 600Z 47 F 5.76k + 100pF NPO 5.76k 120pF NPO
11k
237
OP275
ADCxN 1nF NPO 100pF NPO 1nF NPO
VBIAS (2.25V)
3.01k 11k 270pF NPO
68pF NPO
VREF
OP275
604 560pF NPO OUTx 5.62k 5.62k 1.5k 150pF NPO
AUDIO OUTPUT 2.2nF NPO
5.76k
5.76k
750k 237
OP275
ADCxP
VREF
Figure 18. Typical ADC Input Filter Circuit
Figure 19. Typical DAC Output Filter Circuit
-22-
REV. A
AD1835A
OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52-1)
Dimensions shown in millimeters
1.03 0.88 0.73
2.45 MAX
39
13.45 13.20 SQ 12.95
27 26
SEATING PLANE
40
2.20 2.00 1.80 0.25 MAX
10 6 2
7.80 REF 0.23 0.11 VIEW A 7 0 0.13 MIN COPLANARITY
PIN 1 52 1
TOP VIEW
(PINS DOWN)
10.20 10.00 SQ 9.80
14 13
0.65 BSC
0.40 0.22
COMPLIANT TO JEDEC STANDARDS MS-022-AC.
REV. A
-23-
AD1835A Revision History
Location 12/03--Data Sheet changed from REV. 0 to REV. A. Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Added AD1835A CLOCKING SCHEME section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Added Table II and Table III and renumbered following tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Updated Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated Auxiliary (TDM Mode) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Updated Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Added new Figures 7 and 8 and renumbered subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated Figures 11 and 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Edits to Table XI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Updated Table VIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Updated Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
C03624-0-12/03(A)
Deleted Clock Signals section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
-24-
REV. A
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